Model-based development of digital twins for the early verification and validation of industrial systems.
LieberLieber is part of the European research project MATISSE (Chips Joint Undertaking), on which around 30 partners will be working for three years. It follows on from the EU research project VALU3S, in which LieberLieber convinced all partners of the advantages of modelling with Enterprise Architect and played a key role in the development of the new modelling language VVML. The central theme of MATISSE is the ‘Model-based development of digital twins for the early verification and validation of industrial systems’. Dr Konrad Wieland, CEO of LieberLieber, comments: ‘We are very pleased about the recognition of our contribution to the VALU3S project, which we can now continue and deepen in MATISSE. We are contributing our many years of expertise in the field of software and system modelling as well as the modelling language VVML, which we helped to develop. On this basis, we will work with industry and research partners on the current topic of ‘digital twins’ in concrete application examples. This will give us the opportunity to make a contribution to strengthening Europe’s technological sovereignty and show once again that small and medium-sized enterprises are also important technology drivers in Europe.’
The Austrian MATISSE participants will work together on specific case studies in the project: Dr. Konrad Wieland, Robert Sicher, Danilo Valerio (Siemens), Sashko Ristov (University of Innsbruck)
Everything focusses on digital twins
The main objective of the MATISSE project is to create a framework of methods and tools for the efficient and continuous development and validation of industrial systems supported by digital twins. The aim is to take advantage of model-based, data-driven and cloud techniques to enable validation and verification services that significantly improve productivity and quality. MATISSE aims to enable European research and industry to provide digital twin-based services, including verification, prediction and monitoring, thus improving the overall development and interconnection of digital twins. This effort relies heavily on the use of models and model-based techniques, including both general-purpose languages such as UML/SysML and domain-specific languages (such as VVML) and model transformations. These tools will cover various aspects of the system development process, such as design, modelling quality, test procedures, verification and validation.
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LieberLieber’s objectives in the MATISSE project
LieberLieber expects the MATISEE project to lead to innovations in the following areas:
- Further development and consolidation of the ‘Verification and Validation Modelling Language’ VVML co-developed by LieberLieber
- Modelling of Verification&Validation (V&V) workflows in Enterprise Architect using the VVML framework, which was developed to graphically describe the workflows of V&V methods. This should significantly improve the time and cost of V&V processes.
- Consolidation of expertise and best practice in DevOps for the creation of digital twins
- Further development of LemonTree with regard to automatic versioning and validation processes
MATISSE – A project of the Chips Joint Undertaking
The Chips Joint Undertaking (Chips JU) is a public-private partnership that supports research, development and manufacturing capabilities in the European semiconductor ecosystem. It addresses the semiconductor shortage and strengthens Europe’s technological sovereignty. The Chips JU continues to support the ongoing activities of the Key Digital Technologies Joint Undertaking (KDT JU).
Chips JU continues the predecessor initiative of the Key Digital Technologies KDT JU, i.e. the funding of cooperative transnational R&D projects in the fields of microelectronics, embedded software, smart systems, sub-areas of photonics and current topics such as edge computing and Risc-V. At the same time, the objectives of the first pillar of the European Chips Act will be implemented, i.e. investments in technological capacities such as pilot plants, chips competence centres or a European design platform.
MATISSE is funded as part of the Chips Joint Undertaking (formerly KDT JU) by the Horizon Europe programme of the European Union and the national authorities under the grant agreement 101140216.